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-- This is the XOR block of the single-bit ALU block.
-- Bit width is WORD_SIZE
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
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entity XOR_Block is
	generic( WORD_SIZE : positive);
	port(
		A	:	in 	std_logic_vector(WORD_SIZE-1 downto 0);
		B 	: 	in 	std_logic_vector(WORD_SIZE-1 downto 0);
		S	:	out 	std_logic_vector(WORD_SIZE-1 downto 0)
	);
end XOR_Block;

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architecture Behavioral of XOR_Block is

begin

	S <= A xor B;

end Behavioral;

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